Method and phase-locked loop for synchronization with a subcarrier contained in an intelligence signal

ABSTRACT

To ensure that a phase-locked loop locks quickly to the pilot tone of the stereo-multiplex signal when a new transmitter is tuned in, the stereo-multiplex signal is multiplied in a multiplier M by the quadrature component of the pilot tone generated by a digital oscillator, is low-pass-filtered in a low-pass filter, and is fed as a control signal to the oscillator which is composed of a table of length N and a counter for addressing the table entries. The zero phase angle φ 0  is set by a counter offset n 0  by incrementing or decrementing the counter. It is advantageous to employ a virtual table of length N+ which is larger than the length N of the real table. To access the real table, however, only the corresponding MSBs of the actual count n(k) are used which match the address space of the real table of length N.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to the field of signal synchronization, and in particular to a phase-locked loop for achieving synchronization with a subcarrier contained in an intelligence signal.

DESCRIPTION OF THE RELEVANT ART

[0002] VHF radio transmitters such as FM radio stations broadcast a stereo-multiplex signal that includes a number of components. These components include (i) an audio center signal (also referred to as a mono signal) of up to 15 kHz; (ii) a stereo pilot tone at 19 kHz; (iii) a stereo signal in the 23 kHz to 53 kHz band; (iv) a Motorist Radio Information signal; (v) a narrow-band amplitude-modulated signal at 57 kHz; and (v) a Radio Data System (RDS) signal.

[0003] To demodulate the stereo-multiplex signal, synchronization with the 19 kHz pilot tone is required which serves as an auxiliary carrier. It is desirable for this synchronization to occur as quickly as possible each time a new transmitter is tuned.

SUMMARY OF THE INVENTION

[0004] Briefly, according to one aspect of the invention, a method for synchronizing with a subcarrier contained in an intelligence signal is disclosed. The method comprises the steps of multiplying the intelligence signal by a quadrature component of a subcarrier to generate a first control signal; low-pass filtering the first control signal; and generating the quadrature component of the subcarrier in response to the low-pass filtered first control signal.

[0005] In accordance with another aspect of the invention, a phase-locked loop for synchronization with a subcarrier contained in an intelligence signal is disclosed. The phase-locked loop comprises a digital oscillator having an output at which a quadrature component of the first subcarrier is generated in response to a first control signal; a multiplier having a first input at which the intelligence signal is received and a second input connected to the output of the oscillator, and an output at which a first control signal is generated, the first control signal being the product of the intelligence signal and the quadrature component; and a low-pass filter having an input connected to the multiplier output and an output at which a filtered first control signal is generated, wherein the low-pass filtered first control signal is used to control the digital oscillator.

[0006] In a further aspect of the invention, a phase-locked loop for synchronization with a subcarrier contained in an intelligence signal includes means for multiplying the intelligence signal by a quadrature component of a subcarrier to generate a first control signal; means for low-pass filtering the first control signal; and means for generating the quadrature component of the subcarrier in response to the low-pass filtered first control signal.

[0007] These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

[0008] The FIGURE is a schematic block diagram of one embodiment of a phase-lock loop circuit for synchronizing with a subcarrier contained in an intelligence signal.

DETAILED DESCRIPTION OF THE INVENTION

[0009] The present invention is directed to achieving rapid and precise synchronization with a subcarrier contained in an intelligence signal. Specifically and in accordance with one embodiment, the present invention is directed to synchronizing with an auxiliary carrier of a stereo-multiplex signal. In one particular application, the present invention is directed to a phase-locked loop circuit and method for synchronizing with a 19 kHz pilot tone component of a VHF stereo-multiplex signal. The present invention enables a tuner to demodulate the stereo-multiplex signal by quickly synchronizing with the pilot tone component, which serves as an auxiliary carrier for the stereo-multiplex signal. As will be described in detail below with reference to one particular embodiment, a product of the intelligence signal and a quadrature component of the subcarrier is low-pass filtered and used to control an oscillator to generate the subcarrier quadrature component.

[0010] The FIGURE is a schematic block diagram of one embodiment of a phase-lock loop circuit for synchronizing with a subcarrier contained in an intelligence signal. In the exemplary application, the intelligence signal is a stereo-multiplex signal 102. Phase-lock loop circuit 100 receives stereo-multiplex signal 102. Stereo-multiplex signal 102 is presented at the first input of multiplier 106 the output of which is connected with the input of a low-pass filter 110. As will be described in detail below, an oscillator 114 of phase-lock loop circuit 100 generates a quadrature component 104 of the subcarrier for stereo-multiplex signal 102. In this exemplary application, quadrature component 104 is the 19 kHz pilot tone component of stereo-multiplex signal 102. Quadrature component 104 is applied to a second input of multiplier 106. Stereo-multiplex signal 102 is multiplied by quadrature component 104 (i.e., a 19 kHz pilot tone) at multiplier 106 to generate a first control signal 108. As will be described in detail below, this low-pass filtered control signal 108 is used to control oscillator 114 to generate quadrature component 104.

[0011] First control signal 108 is provided to a low-pass filter 110 which filters first control signal 108. The resulting filtered first control signal 112 is used to control oscillator 114 to generate quadrature component 104 as described below. The output of low pass filter 110 is connected to the input of a loop filter 120. Loop filter 120 generates first and second control signals 122, 124, which are described below. Control signals 122, 124 are provided to an oscillator control circuit 116. In one embodiment, oscillator 114 is a digital oscillator and oscillator control circuit 116 is an arithmetic unit. Oscillator control circuit 116 generates two control signals 126, 118 which are used to control digital oscillator 114 as described below.

[0012] In one embodiment, digital oscillator 114 comprises a look-up table (LUT) of length N and a counter which serves to address the table entries which are preferably integers of n bits each. Control signal 126 generated by oscillator control circuit 116 is a table address increment value, while control signal 118 is a counter offset value. Table increment value 126 is used to determine which entries in the oscillator table are read while counter offset 118 is provided to digital oscillator 102 to increment or decrement the counter to set the zero phase angle φ₀. In one embodiment of the invention, a table entry LUT(n), located at address n, is determined according to equation 1:

(1) LUT(n)=NINT(2^((nbit−1))·sin(2πn/N)),

[0013] where:

[0014] n is an integer between 0 and N−1;

[0015] N is the length of the table;

[0016] nbit is the word length of a table entry; and

[0017] NINT signifies rounding to the next higher integer.

[0018] As noted, in accordance with one embodiment of the present invention, quadrature component 104 is the 19 kHz pilot component. Digital oscillator 114, therefore, preferably generates a sinusoidal quadrature component 104 having a frequency f₀ of 19 kHz. To generate a sinusoidal signal 104 having a frequency of 19 kHz given a scanning frequency of 176.4 kHz, the oscillator table entries are read with an increment Δn 126 that calculated by oscillator control circuit 116 in accordance with equation 2.

(2) Δn=NINT(N·(f ₀ f _(A)))

[0019] Given a table of length N=256, for example, the resulting increment Δn is 110.

[0020] As noted, control signal 118 is a counter offset value that is provided to digital oscillator 102 to increment or decrement the counter to set the zero phase angle φ₀. To set the zero phase angle (φ₀) in the counter, counter offset 118 is calculated in one embodiment of digital control circuit 116 according to equation 3:

(3) n ₀ =NINT((φ₀/2π)·N)

[0021] where, n₀ is the counter offset value.

[0022] In another embodiment of the invention, counter offset 118 is a time-variable offset n₀(k). In this embodiment, the count n(k) at time k*T_(A), where T_(A)=1/f_(A), is calculated by equation 4:

(4) n(k)=(n(k−1)+Δn+n ₀(k)) modulo N

[0023] To minimize any accumulation of rounding errors when calculating the addresses of the table entries, another embodiment provides for a virtual table having a length that is significantly larger than the length N in the actual table. For example, in one embodiment, the length of the virtual table is 64 times as large as the table length N. All calculations of counts and addresses are computed based on the above equations for the virtual table. To access the real table, however, only the corresponding most significant bits of the actual count n(k) are used which match the address space of the real table of length N.

[0024] As noted, first control signal 108 is filtered by low-pass filter 110. In response to low-pass-filtered signal 112, loop filter 120 generates control signals 122, 124. Second control signal y_(p) 122 is proportional to first control signal 108. Loop filter 120 also generates a third control signal y₁ 124 which is averaged over time from first control signal 108. As noted, control signals 122, 124 are provided to an oscillator control circuit 116. In this illustrative embodiment, oscillator control circuit 116 is an arithmetic unit that calculates the offset n₀(k) for the counter of digital oscillator 114 from second control signal y_(p) 122 and third control signal y₁ 124 according to the equation 5:

(5) n ₀(k)=NINT(c _(p) ·y _(p)−/2π)÷c ₁ ·y ₁·(N˜/2π))

[0025] In equation 5, the constants c_(p) and c₁ regulate the control response of phase-locked loop 100. Based on an appropriate selection of these constants c_(p) and c₁, the phase-locked loop may be controlled in a manner analogous to that of a program identification (PI) controller. Since control of the phase of the pilot tone 104 Generated by oscillator 114 is performed via the time-variable offset n₀(k), a similarly time-variable increment is produced for access to the table of the counter.

[0026] To reduce memory space in the oscillator table, in one embodiment of the invention a quarter period of a sinusoidal signal is stored. It should be appreciated, however, that with this approach, however, is that the resulting calculations of the addresses are more elaborate.

[0027] Synchronization of pilot tone contained in stereo-multiplex signal 102 with pilot tone 104 generated by digital oscillator 114 is achieved as soon as first control signal 108 becomes zero. This is the case when quadrature component 104 of the pilot tone generated by oscillator 114 stands in quadrature to the pilot tone contained in stereo-multiplex signal 102.

[0028] The method according to the invention and phase-locked loop according to the invention are distinguished by the first advantage of fast synchronization. This means that the phase-locked loop according to the invention locks in quickly. A second advantage of the method according to the invention is that the method may be implemented through software.

[0029] As noted, the present invention can be utilized to achieve rapid and precise synchronization with a subcarrier contained in an intelligence signal. In the exemplary application described above, the present invention is directed to synchronizing with an auxiliary carrier of a VHF stereo-multiplex signal. As one of ordinary skill in the art would appreciate, the synchronization approach of the present invention can be implemented in conjunction with any tuner now or later developed to enable the tuner to demodulate an intelligence signal such as the noted stereo-multiplex signal. The present invention is particularly well-suited for stereo radio receivers, specifically car radios.

[0030] Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.

[0031] What is claimed is: 

1. A method for synchronizing with a subcarrier contained in an intelligence signal., comprising the step of: multiplying the intelligence signal by a quadrature component of a subcarrier to generate a first control signal; low-pass filtering the first control signal; and generating the quadrature component of the subcarrier in response to the low-pass filtered first control signal.
 2. The method according to claim 1, wherein an oscillator is utilized to generate the quadrature component of the subcarrier, wherein the oscillator comprises: a table of length N; and a counter which serves to access the table entries, the counter having a count beginning at a specified offset and incrementing at a specified increment.
 3. The method according to claim 2, wherein the table entries are integers of n bits each:
 4. The method of claim 2, wherein the step of generating the quadrature component of the subcarrier comprises the step of: reading the table entries at a increment specified in accordance with the filtered first control signal.
 5. The method according to claim 2, wherein the step of generating the quadrature component of the subcarrier comprises the step of: setting the offset of the counter to cause a phase angle in the oscillator to be set to zero.
 6. The method according to claim 4, wherein the step of generating the quadrature component of the subcarrier further comprises the step of: adjusting the counter by an offset n₀ to set a zero phase angle φ₀ in the oscillator prior to reading the table entries.
 7. The method according to claim 2, wherein the method further comprises: forming entries LUT(n) each located at an address n of the table in accordance with the equation: LUT(n)=NINT(2^((nbit−1))·sin(2πn/N)) wherein n is an integer between 0 and N−1; N is the length of the table; nbit is the word length of a table entry; and the operator NINT signifies rounding to the next higher integer.
 8. The method according to claim 4, wherein the subcarrier quadrature component is a sinusoidal signal of frequency f₀ at a scanning frequency of f_(A), and wherein the step of reading the table entries at a increment specified in accordance with the filtered first control signal comprises the step of: determining the specified increment according to the equation: Δn=NINT(N·(f ₀ /f _(A))) wherein operator NINT signifies rounding to the next higher integer.
 9. The method according to claim 5, wherein the step of setting the offset of the counter to cause a phase angle in the oscillator to be set to zero comprises the step of: calculating the offset n₀ of the counter from the zero phase angle φ₀ according to the equation: n ₀ =NINT((φ₀/2π)·N)
 10. The method according to claim 5, wherein the method further comprises the step of: calculating a count of the counter at time k*T_(A), where T_(A)=1/f_(A) and f_(A) is the scanning frequency, according to the equation: n(k)=(n(k−1)+Δn+n ₀(k)) modulo N
 11. The method according to claim 2, wherein the table has a length N and wherein the step of generating the quadrature component of the subcarrier comprises the step of: determining a virtual count offset and increment into a virtual table of length N+ which is larger than the length N of the table, wherein only the corresponding most significant bits of the actual count n(k) are used to access to the table which match the address space of the table of length N.
 12. The method according to claim 1, further comprising the steps of: generating, in response to the low-pass-filtered control signal, a second control signal proportional to the first control signal, and a third control signal which is averaged over time from the first control signal, and calculating the offset n₀(k) of the counter from the second and third control signals according to the equation: n ₀(k)=NINT(c _(p) ·y _(p)−(N˜/2π)+c _(i) y ₁·(N˜/2π)) where c_(p) and c₁ are constants for regulating the control response.
 13. The method according to claim 2, wherein, to reduce the memory requirement in the table of the counter, only a quarter period of a sinusoidal signal is stored.
 14. The method according to claim 1, wherein the method is implemented as software.
 15. The method according to claim 1, wherein the intelligence signal is a stereo-multiplex signal, and wherein the subcarrier is the pilot tone at a frequency of 19 kHz.
 16. A phase-locked loop for synchronization with a subcarrier contained in an intelligence signal comprising: a digital oscillator having an output at which a quadrature component of the first subcarrier is generated in response to a first control signal; a multiplier having a first input at which the intelligence signal is received and a second input connected to the output of the oscillator and an output at which a first control signal is generated, the first control signal being the product of the intelligence signal and the quadrature component; and a low-pass filter having an input connected to the multiplier output and an output at which a filtered first control signal is generated, wherein the low-pass filtered first control signal is used to control the digital oscillator.
 17. The phase-locked loop according to claim 16, further comprising: a loop filter having an input connected to an output of the low-pass filter, the loop filter generating second and third control signals; and an arithmetic unit having first and second inputs at which the second and third control signals are received, the arithmetic unit having first and second outputs connected to control inputs of the oscillator.
 18. The phase-locked loop according to claim 16, wherein the oscillator comprises: a table of length N; and a counter which serves to address the table entries.
 19. The phase-locked loop according to claim 18, wherein the table entries are integers of n bits each.
 20. The phase-locked loop according to claim 18, wherein the table entries are readable with a specified counter increment value.
 21. The phase-locked loop according to claim 18, wherein a zero phase angle in the oscillator is set by incrementing or decrementing the counter by an offset value.
 22. The phase-locked loop according to claim 20, wherein entries LUT(n) each located at an address n of the table in accordance with the equation: LUT(n)=NINT(2^((nbit−1))·sin(2πn/N)) wherein n is an integer between 0 and N−1; N is the length of the table; nbit is the word length of a table entry; and the operator NINT signifies rounding to the next higher integer.
 23. The phase-locked loop according to claim 21, wherein the subcarrier quadrature component is a sinusoidal signal of frequency f₀ at a scanning frequency of f_(A), and wherein the increment at which the table entries are read is determined according to the equation: Δn=NINT(N·(f ₀ /f _(A))) wherein operator NINT signifies rounding to the next higher integer.
 24. The phase-locked loop according to claim 22, wherein the offset n₀ of the counter is calculated from the zero phase angle φ₀ according to the equation n ₀ =NINT((φ₀/2π)·N)
 25. The phase-locked loop of claim 21, wherein the counter increment is calculated at time k*T_(A), where T_(A)=1/f_(A) and f_(A) is the scanning frequency, according to the equation: n(k)=(n(k−1)+Δn+n ₀(k)) modulo N
 26. The phase-locked loop according to claim 24, wherein, in response to the low-pass-filtered control signal, second and third control signals are generated, the second control signal being proportional to the first control signal, and wherein the third control signal is averaged over time from the first control signal, and further wherein the offset n₀(k) of the counter is calculated from the second and third control signals according to the equation: n ₀(k)=NINT(c _(p) ·y _(p)−(N˜/2π)÷c _(i) y _(i)(N˜/2π)) where c_(p) and c₁ are constants for regulating the control response.
 27. The phase-locked loop according to claim 26, wherein the intelligence signal is a stereo-multiplex signal, and the subcarrier is a pilot tone at a frequency of 19 kHz.
 28. A phase-locked loop for synchronization with a subcarrier contained in an intelligence signal comprising: means for multiplying the intelligence signal by a quadrature component of a subcarrier to generate a first control signal; means for low-pass filtering the first control signal; and means for generating the quadrature component of the subcarrier in response to the low-pass filtered first control signal.
 29. The phase-locked loop according to claim 28, wherein the means for generating a quadrature component of the subcarrier comprises: a digital oscillator comprising a table of length N and a counter which serves to access the table entries, the counter having a count beginning at a specified offset and incrementing at a specified increment; and means for reading the table entries at a increment specified in accordance with the filtered first control signal. 